Subject: Re: [Cfrg] AES GCM SIV analysis
From: Adam Langley <[email-masked]>
To: Dan Harkins <[email-masked]>
Cc: "[email-masked]" <[email-masked]>
Date: Fri, 27 Jan 2017 12:21:42 -0800
List-Id: Crypto Forum Research Group <cfrg.irtf.org>

On Thu, Jan 26, 2017 at 6:26 PM, Dan Harkins <[email-masked]> wrote:
>   But that is the definition used in the seminal work on the matter, [1].
> If you want to have a different notion concerning a lesser restriction on
> nonce reuse then you should use a different term.

That paper formalises an advantage that an attacker might have over an
ideal scheme. In the same way that block ciphers aren't ideal PRFs,
nonce-misuse-resistant schemes aren't hitting that ideal either. RFC
5297 doesn't hit it, at minimum because it'll run out of counter-space
after enough messages. AES-GCM-SIV isn't hitting it either.

But that doesn't mean that they aren't practically useful.

I'm not sure what an ideal NMR AEAD would look like, but it's probably
quite different to both RFC 5297 and AES-GCM-SIV and probably looks
like a wide-block construction. If someone can point at something they
think does hit it, that would be interesting to me at least. (Although
perhaps it's well trodden ground for those who are more familiar with
the literature than I.)

>   Which brings up a question I've resisted asking: Why are you doing this?
>
>   If you want to have an AEAD scheme that is nonce-misuse resistant that
> can use a fast(er) authentication scheme then why not just do RFC 5297
> with GHASH instead of AES-CMAC?

AES-GCM has lead to a state of the world where our large machines,
which need to encrypt and decrypt lots of data, end up having hardware
support for AES and GF(128) operations. We would like to take
advantage of that because it's hard to beat the speed and power
efficiency of dedicated hardware, but sometimes we want not to have to
worry about nonces.

> You're defining a new irreducible
> polynomial that, to my knowledge, is not in existing hardware the way
> that PCLMULQDQ using x^128 + x^7 + x^2 + x + 1, is in Intel chips.

PCLMULQDQ (and other hardware implementations, to my knowledge) is not
specific to that polynomial. Also, the polynomial in AES-GCM-SIV is
that polynomial, just with some ordering oddities addressed. See
https://tools.ietf.org/html/draft-irtf-cfrg-gcmsiv-03#appendix-A.

> You're defining a(nother) KDF /inside/ the cipher mode itself instead of
> just letting a KDF, which all users of AES-GCM-SIV will use, generate a
> double-wide key. And I don't see the reason for either.

Our KDF is per-nonce; it's not the same as having a double-width key
and partitioning it internally. We do this in order to get better
bounds when encrypting very large numbers of messages.

Cheers

AGL