IETF Logo Mail Archive

Re: [CFRG] Threshold Sig required - Random bit flip hits Cert Transparency Log

Tim Dierks <tim@dierks.org> Thu, 08 July 2021 15:21 UTC

Return-Path: <tim@dierks.org>
X-Original-To: cfrg@ietfa.amsl.com
Delivered-To: cfrg@ietfa.amsl.com
Received: from localhost (localhost [127.0.0.1]) by ietfa.amsl.com (Postfix) with ESMTP id 4EA2C3A22F4 for <cfrg@ietfa.amsl.com>; Thu, 8 Jul 2021 08:21:28 -0700 (PDT)
X-Virus-Scanned: amavisd-new at amsl.com
X-Spam-Flag: NO
X-Spam-Score: -2.098
X-Spam-Level:
X-Spam-Status: No, score=-2.098 tagged_above=-999 required=5 tests=[BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001] autolearn=ham autolearn_force=no
Authentication-Results: ietfa.amsl.com (amavisd-new); dkim=pass (2048-bit key) header.d=dierks.org
Received: from mail.ietf.org ([4.31.198.44]) by localhost (ietfa.amsl.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sRGaWrM18rdW for <cfrg@ietfa.amsl.com>; Thu, 8 Jul 2021 08:21:23 -0700 (PDT)
Received: from mail-yb1-xb2f.google.com (mail-yb1-xb2f.google.com [IPv6:2607:f8b0:4864:20::b2f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ietfa.amsl.com (Postfix) with ESMTPS id 3A1553A22F3 for <cfrg@irtf.org>; Thu, 8 Jul 2021 08:21:22 -0700 (PDT)
Received: by mail-yb1-xb2f.google.com with SMTP id x192so9532316ybe.6 for <cfrg@irtf.org>; Thu, 08 Jul 2021 08:21:22 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dierks.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=FfciVXOnNU2q1i/+CBXVj9jPdGreF9XEfRf0AjssMA4=; b=L8VD3RL0+81UKROvW9AQHXdCogHg9er4/6NLd7cqMYo0AjYOvzI0IajW8CK801tdQ8 OvAaka5nHRhxniY8dt2h1d2HbfQFurrnbBdXtVmi9ygKacQOwQgeUj9/9hXQD3xKt0Ym o62VaR1X2hy5qjoG/5RoIP4BSg1SOf7Hk2nCUbS6/SFfFfYMQ5CJCD+6lc7FblvzNot4 IErwj2mEVEGV6jNiFBmtdt00enzjwtNNXRsKwgN/W3i7f+CswcOB9bI5T4xJIAUnQZlW MQc80pluYp8hjnzRhLZwrHV59Nq2lABUPGIccgZioeKhdAcMzxqLTw3KxSoYJUsRoq/W 0EUw==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=FfciVXOnNU2q1i/+CBXVj9jPdGreF9XEfRf0AjssMA4=; b=qojL+pQ4wKxzw/lTXhxrKuZbIbuuoyLi8fcLyraImxfqdUKMNQ7gyy04EQ9fbF0ChL DSYb5QihpFui3pLLaC1ZR8RlyK9iG/6kbytB4esaL3uxXprGEJBy8RTb/lDn/aa1cZB5 V3zwQWtWGPkl6pDSn9Bx//z/2J1/gn6BAGjuC67Zh66G3oiDdNmcTf2xYsPvT9nUVuG0 YtQ4XDlT2amu1j0SYvMRquGAmndJxoA5M+JAokewK/100RE8Hi+jyclFaOc+B0CrVgFH aoXZjeyJet2C0G05dH8Y2SieIIqVBr3ddtxnDdeo76sqR5MCD1NpshiXhKkNhZcYkFnK wBMA==
X-Gm-Message-State: AOAM530nqjh+p2eUd9ucQh/Z7bHa+QzyLJE2VBgrjUthP4zrajKEn+BF zjkUBaXB/NpR+Uifc6uLiAyYZNHS0O7IY/MXBdIfyg==
X-Google-Smtp-Source: ABdhPJyWXstBWmVhPbN5A5btaKJTUunsqf7JH1Ooz/kivuWuzrfMwo1LvNY3TpNmDsFD7oL72ZP4x3VRqvadr43l1V8=
X-Received: by 2002:a25:bb08:: with SMTP id z8mr41291751ybg.188.1625757680880; Thu, 08 Jul 2021 08:21:20 -0700 (PDT)
MIME-Version: 1.0
References: <CAMm+Lwjh29Eugv=HO-yL8fXW_xh7a=4vVgCKYWdRvGW9dU9o7A@mail.gmail.com> <CAD5Uzx-JuZVyygfQ8SgmDd5dSWTbE6PXseAUmyThh3dJRdmR_g@mail.gmail.com> <CAMm+LwgfmOh7WTcmTv9FVkAsNz8SLH8ufgNtyRQ6Hgd+TfZGWQ@mail.gmail.com>
In-Reply-To: <CAMm+LwgfmOh7WTcmTv9FVkAsNz8SLH8ufgNtyRQ6Hgd+TfZGWQ@mail.gmail.com>
From: Tim Dierks <tim@dierks.org>
Date: Thu, 08 Jul 2021 11:21:10 -0400
Message-ID: <CAD5Uzx-kMf63ULUifiRvAB_SL5_uV-snTT04DLQEbkA8Rtswew@mail.gmail.com>
To: Phillip Hallam-Baker <phill@hallambaker.com>
Cc: IRTF CFRG <cfrg@irtf.org>
Content-Type: multipart/alternative; boundary="0000000000000f65b105c69e3582"
Archived-At: <https://mailarchive.ietf.org/arch/msg/cfrg/TZPc5LFZWO-4tFJ09qmJlySuJLw>
Subject: Re: [CFRG] Threshold Sig required - Random bit flip hits Cert Transparency Log
X-BeenThere: cfrg@irtf.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: Crypto Forum Research Group <cfrg.irtf.org>
List-Unsubscribe: <https://www.irtf.org/mailman/options/cfrg>, <mailto:cfrg-request@irtf.org?subject=unsubscribe>
List-Archive: <https://mailarchive.ietf.org/arch/browse/cfrg/>
List-Post: <mailto:cfrg@irtf.org>
List-Help: <mailto:cfrg-request@irtf.org?subject=help>
List-Subscribe: <https://www.irtf.org/mailman/listinfo/cfrg>, <mailto:cfrg-request@irtf.org?subject=subscribe>
X-List-Received-Date: Thu, 08 Jul 2021 15:21:28 -0000

On Thu, Jul 8, 2021 at 12:54 AM Phillip Hallam-Baker <phill@hallambaker.com>
wrote:

> If you have a single CPU, you will always have the possibility of an
> error. Not all faults are transient. If the data was corrupted in
> the cache, it is going to be corrupted both times it is hashed. And
> optimizing compilers can screw you in really imaginative ways.
>

We will always have errors, that's the reason we have to take care. But I
believe that errors like this can be detected and prevented from being
committed/released using relatively straightforward redundant checks as
illustrated. If you can identify in the flow described where a bit error
could occur without detection, I'd be interested to know; we're protecting
a lot of data using similar designs. The failure of a reproducible log is
one thing; I'm very interested in avoiding errors when wrapping keys that
might lead to large quantities of data being unrecoverable if not detected
prior to commit.

 - Tim

v2.23.0 | Report a Bug | By Email