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Re: [Cfrg] ECC reboot

Andy Lutomirski <luto@amacapital.net> Thu, 23 October 2014 18:29 UTC

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From: Andy Lutomirski <luto@amacapital.net>
Date: Thu, 23 Oct 2014 11:22:02 -0700
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To: Phillip Hallam-Baker <phill@hallambaker.com>
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Subject: Re: [Cfrg] ECC reboot
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On Thu, Oct 23, 2014 at 11:17 AM, Phillip Hallam-Baker
<phill@hallambaker.com> wrote:
>
>
> On Thu, Oct 23, 2014 at 1:49 PM, Andy Lutomirski <luto@amacapital.net>
> wrote:
>>
>> On Thu, Oct 23, 2014 at 10:41 AM, Alyssa Rowan <akr@akr.io> wrote:
>> >> How long do you think it would take to make an HSM that supports
>> >> our choice?
>> >
>> > Depends: from what I've seen a few HSMs are flexible enough to run
>> > whatever we choose. (I'll refrain from discussion of specific vendors:
>> > it is for them to speak up if they wish.)
>>
>> This seems like a good time to point out that Intel SGX is coming
>> soon.  With SGX, some performance-critical HSM applications could be
>> replaced with hardware-assisted secure *software* enclaves on
>> supported Intel chips.
>>
>> For this application, the relevant factors will be software speed
>> (because it's just x86 software), freedom from timing attacks, and
>> freedom from secrets being leaked in memory access patterns.
>>
>> Some users might require certification, but there will be no
>> additional hardware development effort whatsoever to add new curves.
>
>
> And the AVX-512 extensions provide 512 bit native registers.
>

I feel like you're arguing against a straw man here.  Unless I
misunderstand, the fastest implementations of 512-bit curves don't fit
in 512-bit registers either.

Ed448-goldilocks, on the other hand, might.  Mike?

> I don't think it very likely we can persuade any chip vendor to lay down
> extra signal lines for 521 bits and if they did a 1024 bit data path we
> would be looking at using all of it, not just 9 extra bits.

Wait, what?  Are you suggesting using primes closer to 1024 bits?
That seems even more excessive that 512 or 521 bits.

--Andy

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