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Re: [COSE] [Rats] RAM requirements for COSE/CWT

Laurence Lundblade <lgl@island-resort.com> Mon, 21 February 2022 16:07 UTC

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From: Laurence Lundblade <lgl@island-resort.com>
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Date: Mon, 21 Feb 2022 08:07:45 -0800
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Cc: Anders Rundgren <anders.rundgren.net@gmail.com>, "rats@ietf.org" <rats@ietf.org>, "cose@ietf.org" <cose@ietf.org>
To: Hannes Tschofenig <Hannes.Tschofenig@arm.com>
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Subject: Re: [COSE] [Rats] RAM requirements for COSE/CWT
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On Feb 21, 2022, at 6:31 AM, Hannes Tschofenig <Hannes.Tschofenig@arm.com> wrote:
> 
> I could, however, imagine to write an COSE implementation that does not require the entire CWT be held in RAM since the digital signature just covers the hash of the CWT and you can use a rolling hash.



No need to imagine. For signing, t_cose  <https://github.com/laurencelundblade/t_cose>allows you to create COSE headers, then CBOR-encode the payload an item at a time and then append the signature. t_cose does require the completed COSE message be in RAM, but not the input payload.

LL

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