Re: [Dime] Éric Vyncke's No Objection on draft-ietf-dime-group-signaling-13: (with COMMENT)

[Marco Liebsch <[e-mail]>]

Thanks a lot for your comments, Éric. Please find our feedback inline [ml] below.


-----Original Message-----
From: Éric Vyncke via Datatracker <[e-mail]> 
Sent: Dienstag, 2. Februar 2021 12:19
To: The IESG <[e-mail]>
Cc: [e-mail]; [e-mail]; [e-mail]; [e-mail]
Subject: Éric Vyncke's No Objection on draft-ietf-dime-group-signaling-13: (with COMMENT)

Éric Vyncke has entered the following ballot position for
draft-ietf-dime-group-signaling-13: No Objection

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COMMENT:
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Thank you for the work put into this document. Like Barry and other ADs, I found this document difficult to read: long and complex sentences do not help the reader (but I am not a native English speaker). Therefore, I trust the responsible AD for the correctness of all the details in the specification.
E.g., FSM or time line diagrams would have been helpful.

[ml] We address Barry's and other ADs' comments in separate eMails and also discussed between co-authors where and how to improve some description in revision 14.
 

Please find below some non-blocking COMMENT points (but replies would be appreciated), and some nits.

I hope that this helps to improve the document,

[ml] absolutely.

Regards,

-éric

== DISCUSS ==

== COMMENTS ==

Any reason why the authors affiliation is not shown ?

[ml] no particular reason, only a change of affiliation in one case. Missing information will be added to revision 14.


The shepherd write-up is dated back in 2018... Is it still applicable ?

[ml] yes, Jouni's comments have been addressed at that point in time and we built on that version to address Ben's comments. Despite some delay, the draft progresses according to the defined procedure.


-- Section 7.2 --
About the flag bits, I wonder why the values are not 0x01 and 0x02 rather than
0x01 and 0x10. Isn't this a waste of bits ? Should the IANA sub-registry for those flags be mentioned?

[ml] The AVP with type Unsigned32 is treated as bit mask. Two bits for the Session-Group-Control-Vector AVP are defined in the draft, one for the Session-Group-Capability-Vector AVP. 
Combinations of bits in a mask can be set and make sense in some cases, whereas some other combinations don't. For example, clearing the
SESSION_GROUP_STATUS_IND bit while setting the SESSION_GROUP_ALLOCATION_ACTION bit in an intance of a Session-Group-Control-Vector AVP
does not make sense. Since IANA also asked for clarification, we proposed updated text for the IANA considerations section, which will go into revision 14 of the draft.

marco