using Ethernet MIB with SEEQ 8005/80C04 chips

Steve Tarr <stevet@pink.wv.tek.com> Fri, 06 August 1993 19:01 UTC

Message-Id: <9308061818.AA17609@pink.WV.TEK.COM>
To: kasten@ftp.com
Cc: enet_mib@ftp.com
Subject: using Ethernet MIB with SEEQ 8005/80C04 chips
Date: Fri, 06 Aug 1993 11:18:44 -0700
Sender: ietf-archive-request@IETF.CNRI.Reston.VA.US
From: Steve Tarr <stevet@pink.wv.tek.com>

I'm instrumenting an Ethernet driver for the SEEQ 8005 and SEEQ 80C04
chips (two different controllers, not a two-chip set).  I've found a
few places where the Ethernet MIB (RFC 1398) isn't a good match to the
hardware.  I'm looking for guidance on what to do in these cases and
information on future plans for the MIB.

1) These chips aren't listed in dot3ChipSets.  Is there any procedure
for adding new chips to the standards?

2) The hardware detects "runt" (under-minimum-length) packets and
alignment errors independently of CRC errors, but the MIB only has
counters for CRC-error-without-alignment-error (dot3StatsFCSErrors)
and CRC-error-with-alignment-error (dot3StatsAlignmentErrors).
Is there any way to distinguish between runt packets (with CRC errors)
and normal-length packets with CRC errors?  Is there any way to count
packets with alignment errors but no CRC errors?

3) The hardware doesn't distinguish between single collisions and multiple
collisions on transmit.  Should I count all collisions in
dot3StatsMultipleCollisions or put the collision counter in an
enterprise MIB?

Please send comments directly to me, as I'm not a regular subscriber
to this mailing list.  Thanks,

    Stephen Tarr
    stevet@pogo.wv.tek.com

using Ethernet MIB with SEEQ 8005/80C04 chips Steve Tarr