Re: [Lsr] Flow Control Discussion for IS-IS Flooding Speed

Peter Psenak <ppsenak@cisco.com> Wed, 19 February 2020 19:42 UTC

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To: tony.li@tony.li
Cc: Les Ginsberg <ginsberg@cisco.com>, "lsr@ietf.org" <lsr@ietf.org>
References: <5b430357-56ad-2901-f5a8-c0678a507293@cisco.com> <4FC90EB2-D355-4DC5-8365-E5FBE037954E@gmail.com> <f5b56713-2a4d-1bf7-8362-df4323675c61@cisco.com> <4D5A06BB-0522-4FB5-B783-4AD7C78F8EC0@tony.li>
From: Peter Psenak <ppsenak@cisco.com>
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Date: Wed, 19 Feb 2020 20:42:16 +0100
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Subject: Re: [Lsr] Flow Control Discussion for IS-IS Flooding Speed
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Tony,

On 19/02/2020 20:25, tony.li@tony.li wrote:
> 
> Peter,
> 
>> I'm not scared of polynomial evaluation, but the fact that my IGP 
>> implementation is dependent on the PD specifics, which are not 
>> generally available and need to be custom built for each PD 
>> specifically. I always thought a good IGP implementation is PD agnostic.
> 
> 
> Your implementation is always dependent on the underlying hardware.  We 
> have timers, we have filesystems, we have I/O subsystems, threads, and 
> clocks to contend with. 

none of the above is dependent on the LC specific hardware.

> The input queue in the hardware is a fact of 
> life and knowing about it can improve our implementations.
> 
> Because the PD layer can provide isolation from the specifics, the IGP 
> implementation is reasonably abstracted from those specifics, in much 
> the same way that the OS has abstracted us from the remainder of the 
> underlying hardware. All I’m proposing is adding one more item to that 
> PD abstraction.

easy to say with a single PD. If you have 20, each with a different 
architecture, it becomes a different problem.

thanks,
Peter


> 
> Regards,
> Tony
>