[mpls] Re: Working Group Last Call on draft-ietf-mpls-mna-hdr (2nd WG call)

[Michael Menth <[e-mail]>]

Hi Stewart, all,

Am 08.10.2024 um 17:18 schrieb Stewart Bryant:
> I can never work out the validity of P4 observations. My impression is that P4 implementations are too restricted by the capabilities of P4 itself.

I don't object. But that's why a running P4 prototype is an indicator 
that a specification is likely not too complex for more flexible 
hardware. And exactly that's the research outcome -an academic 
feasibility study. Manufacturers can do probably much better.

Regards, Michael


> I am not sure how many (if any) mainstream implementations use P4, or how many P4 implementation issues raised are fundamental reflections on the shortcomings of P4.
>
> It would be great to hear from the pure hardware and hardware assisted microcode designers on the design of ISD and PSD MNA.
>
> - Stewart
>
>
>> On 8 Oct 2024, at 15:40, Joel Halpern <[e-mail]> wrote:
>>
>> I would be happy to hear from the hardware engineers.  The one set of folks who were working near that level who have reported indicated that the revisions to the draft addressed their concerns (the P4 prototype.)  I have tried to ask hardware folks to speak up.
>>
>> In the absence of such input however, the reports from those who have talked to them seems much better than my intuition, or other software engineer's opinions.
>>
>> Yours,
>>
>> Joel
>>
>> On 10/8/2024 10:28 AM, Stewart Bryant wrote:
>>> I would really like to hear from the h/w engineers first hand, rather than be told that "they looked at it”.
>>>
>>> Without that interaction it is difficult to make an objective decision on a significant design change to MPLS.
>>>
>>> - Stewart
>>>
>>>
>>>> On 7 Oct 2024, at 16:50, Joel Halpern <[e-mail]> wrote:
>>>>
>>>> I am sure that this change is trivial for some hardware.  What is not obvious is that it is trivial for a sufficiently large portion of the hardware that the imposition of the extra complexity and / or development passes makes sense.  We have been told that hardware engineers looked at and improved the design.  I try not to pretend to expertise I do not have.
>>>>
>>>> Yours,
>>>>
>>>> Joel
>>>>
>>>> On 10/7/2024 10:52 AM, Stewart Bryant wrote:
>>>>> Joel
>>>>>
>>>>> The hardware at the point of decision is having to check for other triggers, so the check is not unique. How much of a burden is it to make both the  32bit and 64bit check in parallel?
>>>>>
>>>>> I suspect in the scheme of things the extra gates needed  would be trivial.
>>>>>
>>>>> Stewart
>>>>>
>>>>>
>>>>>
>>>>>> On 7 Oct 2024, at 3:42 PM, Joel Halpern <[e-mail]> wrote:
>>>>>>
>>>>>> I understand the driver for suggesting experimental.  However, I am little concerned by this approach.  This forwarding is presumably typically supported in hardware.  While some hardware will have the identification adjustable, it does not seem at all clear that all, or even most, hardware will have that flexibility.   Asking implementors to respin software is something we do all the time, and is quite reasonable.  But asking folks to respin behavior that may be embedded in ASIC chips is both a major imposition and a significant backwards compatibility problem.
>>>>>>
>>>>>> thus, while I sympathize with the suggest, I think we really need to publish this draft promptly as a Proposed Standard if we expect folks to implement it.
>>>>>>
>>>>>> Yours,
>>>>>>
>>>>>> Joel
>>>>>>
>>>>>>
>>>>>>> On 10/7/2024 10:31 AM, Stewart Bryant wrote:
>>>>>>> I have been thinking the same.
>>>>>>>
>>>>>>> Hop by hop changes of this magnitude are a big deal.
>>>>>>>
>>>>>>> The safest option would be to run it as experimental protocol on an ESPL. That way we can learn more about the design and its properties and if we need to make a change we have plenty more ESPLs
>>>>>>>
>>>>>>> If the experiment succeeds we can move to PS with a BSPL.
>>>>>>>
>>>>>>> Stewart
>>>>>>>
>>>>>>>>> On 7 Oct 2024, at 10:13 AM, IJsbrand Wijnands <[e-mail]> wrote:
>>>>>>>> Dear MPLS WG,
>>>>>>>>
>>>>>>>> Given the nature of the changes to the MPLS architecture for supporting ISD in the data-plane, and the various concerns that have raised on the list, I believe that this document should be on the experimental track.
>>>>>>>>
>>>>>>>> I do not support publishing this document on standards track.
>>>>>>>>
>>>>>>>> Thx,
>>>>>>>>
>>>>>>>> Ice.
>>>>>>>>
>>>>>>>>> On 24 Sep 2024, at 15:25, Tarek Saad <[e-mail]> wrote:
>>>>>>>>>
>>>>>>>>> Dear WG,
>>>>>>>>>
>>>>>>>>> This email starts a two-week Working Group last call for draft-ietf-mpls-mna-hdr. This is the 2nd WG last call for this document.
>>>>>>>>> Please indicate your support or concern for this draft. If you are opposed to the progression of the draft to RFC, please articulate your concern. If you support it, please indicate that you have read the latest version, and it is ready for publication in your opinion. As always, review comments and nits are most welcome.
>>>>>>>>>
>>>>>>>>> Please send your comments to the mpls WG mailing list ([e-mail])
>>>>>>>>> If necessary, comments may be sent unidirectional to the WG chairs.
>>>>>>>>>
>>>>>>>>> Note, currently there are 5 IPR disclosures against this document at https://datatracker.ietf.org/ipr/search/?submit=draft&id=draft-ietf-mpls-mna-hdr
>>>>>>>>>
>>>>>>>>> This poll runs until October 8, 2024.
>>>>>>>>>
>>>>>>>>> Thank you,
>>>>>>>>> Tarek (for the MPLS WG co-chairs)
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-- 
Prof. Dr. habil. Michael Menth
University of Tuebingen
Faculty of Science
Department of Computer Science
Chair of Communication Networks
Sand 13, 72076 Tuebingen, Germany
phone: [phone]
mailto:[e-mail]
http://kn.cs.uni-tuebingen.de