[nmrg] Using bottleneck structures to model larger scale networks
Jordi Ros Giralt <jros@qti.qualcomm.com> Thu, 14 July 2022 10:24 UTC
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From: Jordi Ros Giralt <jros@qti.qualcomm.com>
To: "nmrg@irtf.org" <nmrg@irtf.org>
Thread-Topic: Using bottleneck structures to model larger scale networks
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Date: Thu, 14 Jul 2022 10:24:05 +0000
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Subject: [nmrg] Using bottleneck structures to model larger scale networks
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Hi all, The latest version of draft-irtf-nmrg-network-digital-twin-arch (https://datatracker.ietf.org/doc/draft-irtf-nmrg-network-digital-twin-arch/) references two papers ([G2-SIGCOMM], [G2-SIGMETRICS]) we co-authored to illustrate how bottleneck structures can be used to help model networks at a scale that would not be feasible to model with a simulator or an emulator. Qin Wu reached out to me suggesting if I could provide a paragraph description on how bottleneck structures can be used. You will find my paragraph contribution in Section 7.2 of the draft. He also suggested that I write an email to this list to help open up this conversation and help with any comments or questions, if any. Feel free to do so over this email thread. We are currently looking into bringing bottleneck structures to the ALTO WG where we are active. Using this framework to help build the digital twin is also an area where we are interested. I will be in the Philadephia so I look forward to attending the NMRG sessions and meet some of you. Thanks, Jordi
- [nmrg] Using bottleneck structures to model large… Jordi Ros Giralt