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Re: Hardware acceleration and packet number encryption

Mikkel Fahnøe Jørgensen <mikkelfj@gmail.com> Sat, 24 March 2018 16:52 UTC

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From: Mikkel Fahnøe Jørgensen <mikkelfj@gmail.com>
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Date: Sat, 24 Mar 2018 12:52:47 -0400
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Subject: Re: Hardware acceleration and packet number encryption
To: Christian Huitema <huitema@huitema.net>
Cc: "Deval, Manasi" <manasi.deval@intel.com>, IETF QUIC WG <quic@ietf.org>
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Below ...

On 24 March 2018 at 14.28.21, Mikkel Fahnøe Jørgensen (mikkelfj@gmail.com)
wrote:

Both AES and chachapoly allows up to 96-bit nonce, while we only use 64
bits. Remaining 32 bits are left zero. In that space, we can store
path-id (that
is incremented by one for every new path) to avoid nonce-reuse.


This is the same concept as segmented packet number except the lower PN
bits are encrypted. But if you send three packets in a row on the same path
with a new path id, it is not very difficult to make a qualified guess
about the unencrypted packet number. So why bother encrypting in the first
place using this approach?

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