RE: Hardware acceleration and packet number encryption

[Mikkel Fahnøe Jørgensen <[e-mail]>]

I can live with packet number encryption in v1 if it opens up for
unencrypted multipath multi PN spaces in v2. This in turn, we solve the
issue with single pass hardware for v2 - since there is then no encryption.

However, I strongly suggest that it is done in a way that does not require
buffer modification for encryption. That means the the packet number cannot
be part of the AEAD data. It is also not difficult to avoid - see my
comments added to PR 1079.

As to 64-bit encryption - I seriously doubt this is worthwhile -
non-standard, takes up space, dubious security given enough power, and
again, it is not necessary because you can encrypt packet numbers down to a
single byte if you keep the PN out fo the AEAD data. Please provide a
counter argument if you think that this is not correct:
https://github.com/quicwg/base-drafts/pull/1079#issuecomment-376165638

The only issue I see is whether the PN should be placed first or last - and
if hardware acceleration is not the target for v1, it should be placed last..

- and again, I think it is futile to encrypt packet numbers for linkability
protection, but as I said, if it opens up for V2 without it, please by all
means, let's get this over with. Just don’t require in-place buffer updates
or buffer copies before verification and decryption. It is not necessary.

Kind Regards,
Mikkel Fahnøe Jørgensen


On 31 March 2018 at 18.21.48, Praveen Balasubramanian (
pravb=[e-mail]) wrote:

PNE is actually PNT (packet number transform) as I recall Jana had pointed
out in the early discussions. Encryption is just one possible transform to
apply to the actual PN before putting it in the clear portion of the
header. There are other possible transforms like increment, XOR, and no-op.
Preventing linkability seems to require encryption but I am not convinced
that it actually provides unlikability or is worth the extra computation
cost per packet. Can someone please clarify how it prevents a simple attack
like looking at timing of failovers to link IP addresses? Preventing
ossification requires a transform that does some form of greasing. If we go
down the path of negotiation for the transform, the client initial PN will
need to be random and treated specially just like the CID and there are
likely some other gotchas I haven’t thought of.

Thanks

-----Original Message-----
From: QUIC [mailto:[e-mail]] On Behalf Of Praveen
Balasubramanian
Sent: Wednesday, March 28, 2018 7:47 PM
To: Watson Ladd <[e-mail]>; Ian Swett <[e-mail]>
Cc: Jana Iyengar <[e-mail]>; IETF QUIC WG <[e-mail]>;
huitema <[e-mail]>
Subject: RE: Hardware acceleration and packet number encryption

Sorry for late response just catching up with this thread.

Re. applicability of hardware offload
This is much broader than the datacenter scenario. We rely on TCP offloads
today for performance of all web services even on the front end. TCP
offloads are present pretty much on every server and VM and on by default.
We cannot afford to make the tradeoff of 2x or more increase in CPU cost
for driving the same workload over QUIC as compared to TCP. If QUIC is
being looked at as a general purpose transport and a replacement of TCP,
then hardware offload is absolutely an important requirement. We already
have scenarios in progress that are non-HTTP. Over time the TCP offloads
have also been supported on client systems primarily on Ethernet, but we
have seen recent adoption in Wifi NICs and mobile broadband as well. The
CPU savings are large even at smaller data rates. I'd be happy to publish
the numbers we have around offloads like LSO and LRO.

Re. multiple PN spaces
I am not understanding why this has high implementation cost so please
explain more. For one, this seems to be needed primarily for connection
migration which to me looks like an optional feature of QUIC v1 (not sure
if this is stated as such in the draft but it should be). And
implementations that choose to build connection migration support might as
well do the right design so they are ready for multi-path.

My preference order for different proposed solutions:
1. Multiple PN spaces without PNE.
2. Negotiate PNE and allow implementations to skip it if they do not
support connection migration or multi-path. All datacenter scenarios will
qualify, apps that do not want to use multiple paths will qualify and all
systems that do not have multiple NICs (or paths) will qualify. This will
allow us to make incremental progress and work on better hardware support
over time. Option 2 holds irrespective of single or multiple PN spaces.
3. Any alternative form of PNE that doesn’t cause issues for offloads.
Still not ideal CPU cost wise (for when we cannot offload) but seems to
have other benefits so we can live with it.

Now I understand that leaving PN in the clear may cause ossification issue
but that seems solvable by greasing both the starting PN and subsequently
not always incrementing by 1 in the clear.

Thanks

-----Original Message-----
From: QUIC [mailto:[e-mail]] On Behalf Of Watson Ladd
Sent: Wednesday, March 28, 2018 6:54 PM
To: Ian Swett <[e-mail]>
Cc: Jana Iyengar <[e-mail]>; IETF QUIC WG <[e-mail]>;
huitema <[e-mail]>
Subject: Re: Hardware acceleration and packet number encryption

On Wed, Mar 28, 2018 at 5:39 PM, Ian Swett <ianswett=
[e-mail]> wrote:
> Thanks for the nice summary Jana.
>
> As much as I'd love to have easier crypto HW acceleration, I've ended
> up arriving at the same conclusion. I don't want to bite off the work
> to do proper multipath in QUIC v1, which I think is the only other
> reasonable option of those Christian outlined.
>
> If someone comes up with a way to transform packet number to make it
> non-linkable, but doesn't have the downside of making hardware offload
> difficult, then I'm open to it. But we've been talking about this for
> 2 months without any notable improvements over Martin's PR.
>
> Given we never talk about any issue only once in QUIC, I'm sure this
> will come up again, but for the time being I think #1079 is the best
> option we have.

I am not so sure this is right. Some proposals I've seen upthread:
- Use a 64 bit blockcipher to encrypt the sequence number
- Various online modes that may or may not be a good idea

And another idea I just had:
-Put the encrypted packet number last in the buffer so it gets outputed at
the right time for transmitting hardware, and then have the receiving
hardware copy the bytes to the front before passing it through the
decryptor.

Admittedly I don't understand the constraints on hardware that might be a
problem for these approaches, but I don't think we are quite licked yet.

Sincerely,
Watson
>
>
>
> On Wed, Mar 28, 2018 at 8:03 PM Jana Iyengar <[e-mail]> wrote:
>>
>> A few quick thoughts as I catch up on this thread.
>>
>> I spent some time last week working through a design using multiple
>> PN spaces, and it is quite doable. I suspect we'll head towards
>> multiple PN spaces as we consider multipath in the future. That said,
>> there is complexity (as Christian notes). This complexity may be
>> warranted when doing multipath in v2 or later, but I'm not convinced
>> that this is necessary as a design primitive for QUICv1.
>>
>> We may want to creatively use the PN bits in v2, say to encode a path
>> ID and a PN, for multipath. We want to retain flexibility in these
>> bits going into v2. We've used encryption to ensure that we don't
>> lose flexibility elsewhere in the header, and it follows that we
>> should use PNE to retain flexibility in these bits as well.
>> (Simplicity of design is the other value in using PNE, since handling
>> migration linkability is non-trivial without
>> it.)
>>
>> This leaves the question of HW acceleration being at loggerheads with
>> the design in PR #1079. First, I expect that the primary benefit of
>> acceleration will be in DC environments. Yes, there are some gains to
>> be had in serving the public Internet as well, but I'm unconvinced
>> that this is the driving use case for hardware acceleration. I
>> understand that others may disagree with me here.
>>
>> AFAIK, QUIC has not been used in DC environments yet. I expect there
>> are other things in the protocol that we'd want to change as we gain
>> experience deploying QUIC in DCs. Spinning up a new version to try
>> QUIC within DCs is not only appropriate, I would recommend it. This
>> allows for rapid iterations internally, and the experience can drive
>> subsequent changes to QUIC. It's what *I* would do if I was to deploy
QUIC inside a DC.
>>
>> So, in short, I think we should go ahead with PR# 1079. This ensures
>> that future versions are guaranteed the flexibility to change the PN
>> bits for better support of HW acceleration or multipath or
what-have-you.
>>
>> - jana
>>
>> On Mar 26, 2018 9:41 AM, "Christian Huitema" <[e-mail]>
wrote:
>>
>>
>> On 3/26/2018 8:20 AM, Swindells, Thomas (Nokia - GB/Cambridge) wrote:
>>
>> Looking at
>> https://na01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fen.w
>> ikipedia.org%2Fwiki%2FAES_instruction_set%23Intel_and_AMD_x86_archite
>> cture&data=02%7C01%7Cpravb%40microsoft.com%7C8124554015264408874708d5
>> 95180268%7C72f988bf86f141af91ab2d7cd011db47%7C1%7C0%7C636578852732108
>> 907&sdata=4kf2m4KYai6Gd6j4Vc1nFOpddVaBKP%2FRXRDcBF57JRQ%3D&reserved=0
>> it seems to imply a large range of server, desktop and mobile chips
>> all have a CPU instruction set available to do AES acceleration and
>> other similar operations (other instruction sets are also available).
>>
>> If we are considering the AES instructions then it looks like it is
>> (or at least will be in the near future) a sizeable proportion of the
>> public internet have it to be used.
>>
>>
>> Certainly, but that's not the current debate. PR #1079 is fully
>> compatible with use of the AES instructions. The issue of the debate
>> is that the mechanism in PR #1079 required double buffering, first
>> encrypt the payload, then use the result of the encryption to encrypt
>> the PN. This is not an issue in a software implementation that can
>> readily access all bytes of the packet from memory, but it may be an
>> issue in some hardware implementations that are designed to do just one
pass over the data.
>>
>>
>> -- Christian Huitema
>>
>>
>>
>



-- 
"Man is born free, but everywhere he is in chains".
--Rousseau.