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Re: Big changes in -17

<alexandre.ferrieux@orange.com> Tue, 30 October 2018 10:20 UTC

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Subject: Re: Big changes in -17
To: Martin Thomson <martin.thomson@gmail.com>
CC: QUIC WG <quic@ietf.org>
References: <CABkgnnVFqdx4VYbqT7SztPf8Q+vWMV86VkOHY-4aGSpauNPapg@mail.gmail.com> <851_1540819578_5BD70A7A_851_343_1_0ada4f1d-e8c5-25b5-0e8b-8111ee726ae7@orange.com> <CABkgnnVG6tT_h9AyoOSBd6qy5eRn0EZ4LO_Z+h-cTgj+MkECmA@mail.gmail.com>
Reply-To: Alexandre Ferrieux <alexandre.ferrieux@orange.com>
From: alexandre.ferrieux@orange.com
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Date: Tue, 30 Oct 2018 11:20:07 +0100
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On 10/29/2018 11:35 PM, Martin Thomson wrote:
> On Tue, Oct 30, 2018 at 12:26 AM <alexandre.ferrieux@orange.com> wrote:
>> Do I assume correctly that "the designs discussed" are the following three:
>>
>>   - nothing (no spin bit)
>>   - spin bit alone
>>   - spin bit + VEC
>>
>> Or is there room for other (written) proposals ?
> 
> You should refer to the email from Lars.  I believe that the approach
> they propose only considers "no spin bit" vs. "spin bit alone".

Then, this means that the two reserved bits (0x3 in 1st byte) are out of scope 
for v1, right ?


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