[Rtg-dt-encap-considerations] Alignment and Ethernet encapsulation

Tom Herbert <tom@herbertland.com> Tue, 20 September 2016 16:13 UTC

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From: Tom Herbert <tom@herbertland.com>
Date: Tue, 20 Sep 2016 09:13:27 -0700
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To: "nvo3@ietf.org" <nvo3@ietf.org>, "rtg-dt-encap-considerations@ietf.org" <rtg-dt-encap-considerations@ietf.org>, Sowmini Varadhan <sowmini.varadhan@oracle.com>
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Subject: [Rtg-dt-encap-considerations] Alignment and Ethernet encapsulation
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Hello,

This issue came up on the Linux netdev list. The Oracle engineers are
trying to deal with the ramifications of unaligned IP headers (not
aligned to four bytes) when doing Ethernet encapsulation (VXLAN, GRE
with TEB for instance). The problem is that certain CPU architectures,
such as SPARC (and maybe PowerPC?), do not handle unaligned accesses
very well. Every unaligned access causes a trap to software which
kills any semblance of performance. x86 has shift logic so we don't
see any issues there (except for unaligned accesses across a page
boundary).

The Linux stack is written to assume that IP protocols are properly
four byte aligned and in non-encapsulation cases Ethernet headers are
padded to be 16 bytes. The problem seems to be specific when
performing Ethernet header encapsulation and there is no padding of
the inner Ethernet header like would be done in ETHERIP. Either the
outer or the inner IP headers will be misaligned. There does not seem
to be an easy fix for this without rewriting the stack or doing copies
on every packet.

For new encapsulation protocols please consider the effects of IP
header alignment in the presence of Ethernet encapsulation. Defining
Ethernet encapsulation with the two byte padding like in ETHERIP may
help a lot to make implementation of Ethernet encapsulation feasible
on CPU HW.

Thanks,
Tom