Re: [TLS] [Cfrg] 3DES diediedie

[Joachim Strömbergson <[e-mail]>]

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Aloha!

Hilarie Orman wrote:
>> On 31 August 2016 at 20:48, Hilarie Orman
>> <[e-mail]> wrote:
> 
>>>> From: Brian Sniffen <[e-mail]>
> 
>> The question is not "how much hardware?" but "price?" - with  ARMs 
>> including h/w AES coming in at $2 for a single unit, its hard to
>> explain why you\d want to use a less powerful CPU...
> 
> 
> Power.
> 
> Hilarie

Did you look at the ARM Cortex M0+ Gecko Zero I pointed to? I'd
recommend that you compare its power consumption to a PIC.

The PIC is manufactured using larger geometries that consumes more
power/gate/MHz. The Gecko Zero has more power modes allowing it to
enable/disable different functions very fast, and is able to scale its
own internal clock frequency very flexibly. The Gecko Zero (and other
M0+ devices) can also do more/cycle so that total power up time is
shortened, saving power.

Specifically (since we talked about it before), the AES core in the
Gecko Zero takes about 50 cycles to process one block (and the CPU core
can be powered down at the same time). Googling for cycles to perform
AES on PIC I found:

Encryption
PIC16F877 : 3834 cycles
PIC16F84 : 7157 cycles

https://edipermadi.wordpress.com/2008/02/09/an-aes-implementation-on-pic16f877/

So on the PIC you need to have the CPU core powered up and running about
80 times longer (in terms of cycles) than the Gecko needs to run its AES
core.

And even if you don't have an AES core, the ARM can do AES in fewer
cycles. This one shows 2270 cycles for AES-128

http://www.cryptovia.com/ARM_Thumb_AES.html


Selecting 8/16 bit MCUs like AVR, PIC, 8051 in 2016 for power reasons
without looking at modern 32-bit MCUs based on ARM or MIPS is a mistake
imho.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          [e-mail]
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