Re: [trill] Alissa Cooper's Discuss on draft-ietf-trill-smart-endnodes-10: (withDISCUSS and COMMENT)

Alissa Cooper <alissa@cooperw.in> Wed, 07 March 2018 15:02 UTC

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From: Alissa Cooper <alissa@cooperw.in>
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Date: Wed, 7 Mar 2018 10:01:50 -0500
Cc: IESG <iesg@ietf.org>, draft-ietf-trill-smart-endnodes@ietf.org, trill-chairs@ietf.org, shares@ndzh.com, trill@ietf.org
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Subject: Re: [trill] Alissa Cooper's Discuss on draft-ietf-trill-smart-endnodes-10: (withDISCUSS and COMMENT)
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Hi Fangwei,

As I noted in response to the Gen-ART reviewer, I managed to ballot before reading the rest of this thread (sorry!), but I still think the diagram in 4.3 is confusing and not consistent with the text. To my eye row 3 shows two bytes’ worth of fields but the label says “4 bytes.” RSV is depicted as 2 bits but the text says it is 6 bits. The combination of these two inconsistencies makes it hard to know what the actual lengths are supposed to be.

Alissa

> On Mar 7, 2018, at 12:55 AM, hu.fangwei@zte.com.cn wrote:
> 
> Hi,Alissa Cooper
> 
> Thanks for your review and comments. 
> 
> The new version(version 10)  has updated to fix your comments.
> 
> The format of Smart-MAC APP sub-TLV and the text  has been changed to the following:
> 
> The length of F,M,RSV,VLAN/FGL data Label is 4 bytes. and the length of VLAN/FGL Data Label field is 24 bits.
> 
> 
> 
>    +-+-+-+-+-+-+-+-+
>     |Type=Smart-MAC |                  (1 byte)
>     +-+-+-+-+-+-+-+-+
>     |   Length      |                  (1 byte)
>     +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>     |F|M|RSV|  VLAN/FGL Data Label  |  (4 bytes)
>     +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-...+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>     |                          MAC (1)       (6 bytes)                 |
>     +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-...+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>     |                      .................                           |
>     +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-...+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>     |                          MAC (N)       (6 bytes)                 |
>     +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-...+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>                      Figure 3 Smart-MAC APPsub-TLV
> 
> 
>    o  VLAN/FGL Data Label: 24bits.  If F is 1, this field is a 24-bit
>       FGL Data Label for all subsequent MAC addresses in this APPsub-
>       TLV.  Otherwise, if F is 0, the lower 12 bits is the VLAN of all
>       subsequent MAC addresses in this APPsub-TLV, and the upper 12 bits
>       is not used(sent as zero and ignored on receipt).  If there is no
>       VLAN/FGL data label specified, the VLAN/FGL Data Label is zero.
> 
>        
> 
> Regards.
> 
> Fangwei.
> 
> 原始邮件
> 发件人:AlissaCooper <alissa@cooperw.in>;
> 收件人:The IESG <iesg@ietf.org>;
> 抄送人:draft-ietf-trill-smart-endnodes@ietf.org <draft-ietf-trill-smart-endnodes@ietf.org>trill-chairs@ietf.org <trill-chairs@ietf.org>shares@ndzh.com <shares@ndzh.com>trill@ietf.org <trill@ietf.org>;
> 日 期 :2018年03月07日 04:45
> 主 题 :Alissa Cooper's Discuss on draft-ietf-trill-smart-endnodes-10: (withDISCUSS and COMMENT)
> Alissa Cooper has entered the following ballot position for
> draft-ietf-trill-smart-endnodes-10: Discuss
> 
> When responding, please keep the subject line intact and reply to all
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> introductory paragraph, however.)
> 
> 
> Please refer to https://www.ietf.org/iesg/statement/discuss-criteria.html
> for more information about IESG DISCUSS and COMMENT positions.
> 
> 
> The document, along with other ballot positions, can be found here:
> https://datatracker.ietf.org/doc/draft-ietf-trill-smart-endnodes/
> 
> 
> 
> ----------------------------------------------------------------------
> DISCUSS:
> ----------------------------------------------------------------------
> 
> This should hopefully be easy to fix and was pointed out by the Gen-ART
> reviewer:
> 
> All of section 4.3 is confusing as to what the length of the TLV really is.
> Row 3 in the diagram says 2 bytes or 4 bytes, but the number of bits called out
> in bullets 4 and 5 below it don't seem to add up to those things. Maybe it would
> be better to draw a diagram with F=0 and a separate diagram with F=1.
> 
> Please make it clear both in the diagram and in the text what the expected
> lengths of the fields are -- I find it particularly confusing that the number
> of bits pictured doesn't align with the number of bits specified in the text
> per field.
> 
> 
> ----------------------------------------------------------------------
> COMMENT:
> ----------------------------------------------------------------------
> 
> Please also look at the Gen-ART reviewer's other comments.
> 
> 
>