[bmwg] FYI
Tamás Hetényi <tamas.hetenyi@gmail.com> Fri, 22 July 2022 20:05 UTC
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From: Tamás Hetényi <tamas.hetenyi@gmail.com>
Date: Fri, 22 Jul 2022 22:05:27 +0200
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Subject: [bmwg] FYI
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Dear All, My name is Tamas Hetenyi and I work with Gabor Lencse on a new implementation of the siitperf project. The core hardware will be Xilinx FPGA (Ultrascale+ SoC) based and the current experimental phase will be implemented on Xilinx ZCU102 SDK (with small modifications). The SDK can handle 4 SPF+ transceivers with 10GB speed each. In the currently running phase we are implementing the Statefull siitperf and performing measurements to prove the extended performance. In the next phase we are implementing the Stateless version. According to our plan results are expected appr. 2-3 months from now. Best Regards Tamas Hetenyi -- dr. Tamás Hetényi Mobile: +36 70 556 4940 Skype: hetenyi_tamas
- [bmwg] FYI Tamás Hetényi