Re: [Cfrg] AES GCM SIV analysis

[Alex Cope <[e-mail]>]

Thanks for the quick responses to my comments. I should have more carefully
proofread my first message, as I confused bit and byte reflection at
several points, my bad.

I'm in agreement that the bit ordering in POLYVAL is far more better, and
after looking into Montgomery multiplication a bit more, working
modulo x^128 + x^127 + x^126 + x^121 + 1 makes more sense. Consider me
convinced.

-Alex


On Mon, Jan 30, 2017 at 5:04 PM, Shay Gueron <[e-mail]> wrote:

> >>> 1) On X86, no performant implementation of POLYVAL will reduce to
> >>> GHASH, as that would result in unnecessarily byte swapping twice
> >>> then calling PCLMULQDQ.
>
> I suggest to count the number of byte swaps done with AES-GCM-SIV
> optimized implementation on X86 (see the code in my guthub, for example),
> and the number of bye swaps done with AES-GCM (take the OpenSSL example).
> The answers are: 0 for AES-GCM-SIV and 1 per each block (of the message
> and the AAD +1) in OpenSSL.
>
> The identity provided in the spec, relating GHASH and POLYVAL is provided
> for convenience, in case someone chooses to re-use software (or hardware).
> It is not suggesting that the fastest way to compute POLYVAL is through
> GHASH.
>
> The reason is (again) the order of bits inside the bytes. The definition
> of AES-GCM which has this order reversed with respect to the order of bits
> in the bytes of AES input/output.
>
> In fact, although many would think that AES-GCM operates natively in
> GF(2^128) with the reduction polynomial is x^128 + x^7 + x^2 + x + 1, this
> is not the case (unless you are reversing the bits in the bytes of each
> block). AES-GCM is operating in the field represented by the reduction
> polynomial x^128 + x^127 + x^126 + x^121 + 1.
>
> There will be explained in detail in a paper that I will post soon. But
> perhaps the slides in my RWC talk could explain this for now (
> https://crypto.stanford.edu/RealWorldCrypto/slides/gueron.pdf)
>
> Regards, Shay
>
>
> 2017-01-30 23:58 GMT+02:00 Alex Cope <[e-mail]>:
>
>> I'm also unconvinced that defining POLYVAL as modulo x^128 + x^127 +
>> x^126 + x^121 + 1 is better than defining it modulo x^128 + x^7 + x^2 + x +
>> 1.
>>
>> My reasons for thinking that  x^128 + x^7 + x^2 + x + 1 is a better
>> reducing polynomial are:
>> 1) On X86, no performant implementation of POLYVAL will reduce to GHASH,
>> as that would result in unnecessarily byte swapping twice then calling
>> PCLMULQDQ. The same seems true for any implementation in a little-endian
>> machine.
>> 2) If the concern is making a less performance sensitive implantation of
>> GCM-SIV easier to write given a GCM implantation, the relationship between
>> POLYVAL as currently defined and GHASH does help slightly. However,
>> implementing finite field multiplication with POLYVAL'S byte ordering
>> modulo x^128 + x^7 + x^2 + x + 1 given a reference GHASH implementation is
>> quite easy*, and most accidental errors in such implementation will be
>> detected by test vectors.  Thus I don't think the current design choice
>> makes GCM-SIV substantially easier to implement correctly.
>> 3) x^128 + x^7 + x^2 + x + 1 is more 'natural' as as the lexicography
>> first irreducible polynomial.  It seems likely that future work that relies
>> on finite field multiplication will opt to use the byte ordering of POLYVAL
>> because it makes the most sense on little endian machines, and will also
>> reduce modulo  x^128 + x^7 + x^2 + x + 1.  I doubt anyone else will want to
>> use GHASH as currently defined, but if it were defined modulo x^128 + x^7 +
>> x^2 + x + 1, the implementation could be nicely reused. I think that in the
>> long term this will lead to more code reuse than having POLYVAL as a one
>> off finite field representation.
>>
>> If you are strongly concerned reusing dedicated hardware or big-endian
>> implementations of GHASH then the current design makes some sense as a
>> compromise, but I'm unaware of such requirements.
>>
>> Regards
>> -Alex
>>
>> *I did it recently for a table-based implementation. You can look at the
>> patch here: https://patchwork.kernel.org/patch/9428397/
>>
>> On Fri, Jan 27, 2017 at 12:21 PM, Adam Langley <[e-mail]>
>> wrote:
>>
>>> On Thu, Jan 26, 2017 at 6:26 PM, Dan Harkins <[e-mail]>
>>> wrote:
>>> >   But that is the definition used in the seminal work on the matter,
>>> [1].
>>> > If you want to have a different notion concerning a lesser restriction
>>> on
>>> > nonce reuse then you should use a different term.
>>>
>>> That paper formalises an advantage that an attacker might have over an
>>> ideal scheme. In the same way that block ciphers aren't ideal PRFs,
>>> nonce-misuse-resistant schemes aren't hitting that ideal either. RFC
>>> 5297 doesn't hit it, at minimum because it'll run out of counter-space
>>> after enough messages. AES-GCM-SIV isn't hitting it either.
>>>
>>> But that doesn't mean that they aren't practically useful.
>>>
>>> I'm not sure what an ideal NMR AEAD would look like, but it's probably
>>> quite different to both RFC 5297 and AES-GCM-SIV and probably looks
>>> like a wide-block construction. If someone can point at something they
>>> think does hit it, that would be interesting to me at least. (Although
>>> perhaps it's well trodden ground for those who are more familiar with
>>> the literature than I.)
>>>
>>> >   Which brings up a question I've resisted asking: Why are you doing
>>> this?
>>> >
>>> >   If you want to have an AEAD scheme that is nonce-misuse resistant
>>> that
>>> > can use a fast(er) authentication scheme then why not just do RFC 5297
>>> > with GHASH instead of AES-CMAC?
>>>
>>> AES-GCM has lead to a state of the world where our large machines,
>>> which need to encrypt and decrypt lots of data, end up having hardware
>>> support for AES and GF(128) operations. We would like to take
>>> advantage of that because it's hard to beat the speed and power
>>> efficiency of dedicated hardware, but sometimes we want not to have to
>>> worry about nonces.
>>>
>>> > You're defining a new irreducible
>>> > polynomial that, to my knowledge, is not in existing hardware the way
>>> > that PCLMULQDQ using x^128 + x^7 + x^2 + x + 1, is in Intel chips.
>>>
>>> PCLMULQDQ (and other hardware implementations, to my knowledge) is not
>>> specific to that polynomial. Also, the polynomial in AES-GCM-SIV is
>>> that polynomial, just with some ordering oddities addressed. See
>>> https://tools.ietf.org/html/draft-irtf-cfrg-gcmsiv-03#appendix-A.
>>>
>>> > You're defining a(nother) KDF /inside/ the cipher mode itself instead
>>> of
>>> > just letting a KDF, which all users of AES-GCM-SIV will use, generate a
>>> > double-wide key. And I don't see the reason for either.
>>>
>>> Our KDF is per-nonce; it's not the same as having a double-width key
>>> and partitioning it internally. We do this in order to get better
>>> bounds when encrypting very large numbers of messages.
>>>
>>>
>>> Cheers
>>>
>>> AGL
>>>
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>>
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