[DMM] DMM FPC I-D - Implementation

"Bertz, Lyle T [CTO]" <Lyle.T.Bertz@sprint.com> Fri, 26 August 2016 20:00 UTC

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From: "Bertz, Lyle T [CTO]" <Lyle.T.Bertz@sprint.com>
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Thread-Topic: DMM FPC I-D - Implementation
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Date: Fri, 26 Aug 2016 20:00:12 +0000
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Subject: [DMM] DMM FPC I-D - Implementation
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All,

Last week at the Intel Developer Forum in San Francisco (US), Intel and Sprint demonstrated a virtual Evolved Packet Core (vEPC) that included, amongst other features, a SGW and PGW (3GPP functions similar to MAG and LMA). This software

1. Used a Separated Control and Dataplane Node with an intermediate SDN Controller - Opendaylight's Beryllium release.

2. Used IETF DMM FPC-v03 (https://datatracker.ietf.org/doc/draft-ietf-dmm-fpc-cpdp/?include_text=1) for communication of some sessions (others were simulated to ensure we met the demonstration timelines).

The Control and Dataplane software performs well (10Gbps down / 3Gbps up for 250K users) on a single Intel processor's *core* based upon the open source DPDK libraries from Intel. The demonstration shows the promise of separation of Control and Data planes.

We had to deviate quite a bit from the version 03 specification to support 3GPP but version 04 adds the 3GPP model as an option. Many of the general changes in version 04 are influenced by the implementation.

Work is already underway to implement version 04 with several internal changes, e.g. moving from the Opendaylight MD-SAL (model driven) approach to the application driven (AD-SAL) approach, as focus is now on performance. I hope to share more details in the future. As a part of the final version of the FPC I-D we will submit an Implementation Status section in the draft per RFC 7942.

Lyle Bertz
Sprint

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