Re: [Iotops] Adoption call for draft-bormann-iotops-ietf-lwig-7228bis-00

Michael Richardson <mcr+ietf@sandelman.ca> Thu, 11 April 2024 16:36 UTC

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From: Michael Richardson <mcr+ietf@sandelman.ca>
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Date: Thu, 11 Apr 2024 12:35:59 -0400
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Subject: Re: [Iotops] Adoption call for draft-bormann-iotops-ietf-lwig-7228bis-00
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I found this link/diff to be useful to understand what's being proposed:
https://author-tools.ietf.org/diff?doc_1=rfc7228&doc_2=draft-bormann-iotops-ietf-lwig-7228bis-00
I support adoption of this document.  This is exactly what I expect IOTOPS to do.

Some comments:

I found the focus on GPIO pins vs RAM pins to be interesting.
I think that the A/M-class distinction is breaking down already, and I would
like some additional criteria.  The "J"-class seems to just jump in with no
introduction, btw.

 	   *  Microcontroller-class devices (sometimes called "M-class").  These
 	      often (but not always) include RAM and code storage on chip and
 	      would struggle to support more powerful general-purpose operating
 	      systems, e.g., they do not have an MMU (memory management unit).
 	      They use most of their pins for interfaces to application hardware
 	      such as digital in/out (the latter often Pulse Width Modulation
 	      (PWM)-controllable), ADC/DACs (analog-to-digital and digital-to-
 	      analog converters), etc.  Where this hardware is specialized for
 	      an application, we may talk about "Systems on a Chip" (SOC).
 	      These devices often implement elaborate sleep modes to achieve
 	      microwatt- or at least milliwatt-level sustained power usage (Ps,
 	      see below).

 	   *  General-purpose-class devices (sometimes called "A-class").  These
 	      usually have RAM and Flash storage on separate chips (not always
 	      separate packages), and offer support for general-purpose
 	      operating systems such as Linux, e.g. an MMU.  Many of the pins on
 	      the CPU chip are dedicated to interfacing with RAM and other
 	      memory.  Some general-purpose-class devices integrate some
 	      application hardware such as video controllers, these are often
 	      also called "Systems on a Chip" (SOC).  While these chips also
 	      include sleep modes, they are usually more on the watt side of
 	      sustained power usage (Ps).

Section 5, classes of networks.
I think that S0/S1/S2/S3 is useful, but perhaps more critical is whether
multicast is useful/supported/well-emulated or not.
I think that 5.2, should perhaps have an I2 for BT(LE) connected to I9
capable device.  e.g., some smartwatches <-> smartphones.
Also step trackers, heart monitors, blood glucose sensors, ...
(Other smartwatches are I9)

--
Michael Richardson <mcr+IETF@sandelman.ca>   . o O ( IPv6 IøT consulting )
           Sandelman Software Works Inc, Ottawa and Worldwide