[Rats] draft-ietf-rats-architecture-12

[Muhammad Usama Sardar <[e-mail]>]

Dear authors,


Here I would like to share some thoughts on the draft:


Abstract: "a model that is neutral toward processor architectures" As the terminology, topological patterns and even the architecture itself is primarily taken from TCG (e.g., https://trustedcomputinggroup.org/resource/dice-attestation-architecture/), it is trivial that the architecture would hold for TPM. So in my view, interesting case is that of TEEs. In this regard, I would like to see a concrete instantiation of how this model, which is claimed to be neutral to architecture, could model the attestation process in Intel SGX/TDX, for instance. More concretely, how will the core entities (TD QE, VMM, TD, TDX Module, CPU Hardware) in the TD attestation be modeled in the RATS architecture? This will not only help make the concrete example of RATS architecture for a specific TEE, but also make the draft more accessible to people who have familiarity with SGX/TDX remote attestation.


Section 3 (Architectural Overview), Section 4 (Terminology) and Section 5 (Topological Patterns): I think it would be helpful for the readers if original source is clarified that the sections are based on TCG (e.g., https://trustedcomputinggroup.org/resource/dice-attestation-architecture/)


Section 4.1: Attester:

  *   Is it not possible to define Attester somehow without using "Attester" itself in its definition? Mathematically, this should be the case only in recursive definitions.
  *   "extent to which" Is it supposed to be quantitative rather than qualitative?

Cheers,
Usama


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Best Regards,

Muhammad Usama Sardar (M.Sc.)

DAAD Scholarship holder

Chair of Systems Engineering

Institute of Systems Architecture

Faculty of Computer Science
Technische Universität Dresden

Germany

Office: APB 3073

Phone: [phone]

Email: [e-mail]

Website: https://tu-dresden.de/ing/informatik/sya/se/die-professur/beschaeftigte/muhammad-usama-sardar

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