Re: [Suit] Fwd: Firmware Update Paper

Hannes Tschofenig <Hannes.Tschofenig@arm.com> Wed, 04 December 2019 12:26 UTC

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From: Hannes Tschofenig <Hannes.Tschofenig@arm.com>
To: Emmanuel Baccelli <Emmanuel.Baccelli@inria.fr>, "suit@ietf.org" <suit@ietf.org>
Thread-Topic: [Suit] Fwd: Firmware Update Paper
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Date: Wed, 4 Dec 2019 12:26:39 +0000
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Subject: Re: [Suit] Fwd: Firmware Update Paper
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The signature verification was performed with the HACL library (ed25519) on an ARM Cortex-M0+ and took approx. 7 seconds -- so yes, pretty long indeed, in this case.

[SS] Does that scale linearly with image size? Do memory requirements (RAM usage) increase with the image size?


[EB] Not really: in the context of this paper, what is signed (and verified) is a hash of the image, not the image itself.

Adding to what Emmanuel said.

The memory requirements very much depend on the selected crypto implementation (and quite naturally the key size). There is also a relationship between the code size and the speed of execution. Code that has been hand-crafted for the specific MCU tends to be faster and consumes less memory than a generic implementation. This is inline with what is being stated in https://datatracker.ietf.org/doc/draft-ietf-lwig-curve-representations/. Needless to say that type of protection offered by an implementation (e.g., side channel attack resistance, such as resistance against remote timing attacks) has an impact on both code size as well as runtime performance.

It would be interesting to also analyze the heap requirements. As written in the paper, we focused only on the stack size.

Ciao
Hannes


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