Re: [manet] packetbb update idea

"Dearlove, Christopher (UK)" <chris.dearlove@baesystems.com> Thu, 06 July 2017 09:28 UTC

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From: "Dearlove, Christopher (UK)" <chris.dearlove@baesystems.com>
To: Justin Dean <bebemaster@gmail.com>
CC: Henning Rogge <hrogge@gmail.com>, "manet@ietf.org" <manet@ietf.org>
Thread-Topic: [manet] packetbb update idea
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Date: Thu, 06 Jul 2017 09:28:25 +0000
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Subject: Re: [manet] packetbb update idea
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Just to nail this one down.

Justin:
> I don't see how having a bit field would work as the order of the addresses in the address block are not guaranteed to be in any specific order.

As I indicated, that’s not a problem. We don’t assign meaning to positions, but we can use positions. As we do every time an Address Block TLV has an index or two indices.

So considering

A-----B
|    /|
|   / |
|  /  |
| /   |
|/    |
C-----D

Let’s assume the addresses are in order A, B, C, D. (If they change, we change TLV values. Which we potentially have to do any time the order changes anyway.)

I’m going to assume LSB = bit zero indexing because it’s easier to follow. 5444 actually uses MSB = bit zero, to fit network byte order. If we ever get that far we can have a Lilliputian argument.

So with bidirectional links, we simply have a TLV that sets the single-length to 1 (i.e. length to 4) and has values 6, 13, 11, 6. Even better we can do directionality. Let’s assume A to B but not B to A, the rest remaining bidirectional, and let’s assign bits by source (another case where there are two options, and we’d pick what we think is the better one). Now the values are 6, 12, 11, 6.

> My example was meant to be a simple illustration what we are working on contains possibly many more addresses and many more associations.

Even bigger win for the bit vector. The single value size goes up by one for each 8 nodes. But otherwise we need one TLV, not one TLV per connection. You’d have to have a very big, very sparse network to even challenge the bit vector. And then we can use another trick, to partition the network up and use more than one bit vector TLV. We should of course use the bit vector positions within the span of the TLV, so if we have a TLV covering, say, indices 3 to 6, bit 0 (whether LSB or MSB) is address 3, bit 1 is address 4 etc.

Incidentally, wanting to carry a topology isn’t a use case, it’s a consequence of a use case.
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