Re: [mpls] Concerns about ISD

[Haoyu Song <[e-mail]>]

Hi Tony,

As I recall, Kireeti only gave a few words claiming it’s easily implementable, while the other vendors (HW and Cisco) confirmed my analysis with their analysis documented in PPTs (specifically, the bitmap encoded ISD increases both parser size and parsing latency).
I believe detailed analysis based on the solid assumption (e.g., parse-able header depth) is needed to understand the tradeoff. After all, for both old and new hardware, we prefer simpler design for higher performance.

Best regards,
Haoyu

From: mpls <[e-mail]> On Behalf Of Tony Li
Sent: Tuesday, April 12, 2022 7:14 AM
To: Dongjie (Jimmy) <[e-mail]>
Cc: [e-mail]
Subject: Re: [mpls] Concerns about ISD


Hi Jie,

We have had two presentations of hardware analysis.

One on 3/10/2022 and another on 1/27/2022.  What more are you expecting?

[Jie] The analysis we had on 1/27/2022 and 3/3/2022 in the DT showed the overhead and complexity of ISD, and questioned whether ISD is needed or not. The analysis slides are attached in the DT meeting notes.

We are still missing equivalent hardware analysis from the proponents of draft-kompella-mpls-mspl4fa. Without that, it is hard to tell whether the proposal is implementable with existing or new hardware, and what would be the cost.


That was the presentation on 3/10.

As I recall, the result was that it was easily implementable, but the recommendation was to replace continuation bits with length fields.

T