Re: [Ntp] Antw: Re: Antw: Re: Antw: [EXT] Re: NTPv5 draft

[Hal Murray <[e-mail]>]

[e-mail] said:
> Is that pure theory, or actual measurements? I mean you'll have to do either
> memory-mapped I/O which won't be cached (hopefully), or you'll have to read I/
> O ports. Or do you talk about something inside the CPU? If so that may have
> high precision until the CPU goes to power saving or whatever. 

Intel has an instruction, rdtsc, that reads the TSC register.  It counts 
cycles.  Early implementations had problems since it counted CPU cycles rather 
than counting at a constant rate.  Those have all been sorted out.  It takes a 
long time to read it.  I don't know the details of what happens on SMP systems.
  https://en.wikipedia.org/wiki/Time_Stamp_Counter

There is some shared memory.  vdso is the buzzword.  There is a man page.

If the shared memory has a time stamp, and a TSC reading for that time, and a 
scale factor that turns TSC ticks into nanoseconds, you can compute the time as
  (newTSC-oldTSC)*scale + base_time.
There is some interesting hacking required to maintain precision and avoid 
overflow and such.  (And more hacking to avoid a race condition when things 
get updated.)

The similar instruction on ARM is illegal in user mode unless you turn on a 
magic bit.  I have no idea why.  Maybe some kernel option turns it on by now.  
Or maybe it was MIPS.  ????

----------

>> So the clock is ticking at somewhere between 2 and 53 ns.
> Where did you get that 2 from? Assuming your read delay is between 50 and

Typo.  It should be 52

> (Raspberry Pi 3 Model B running Fedora aarch64)
>         ns      hits
>         52    497520
>         53     45070
>        104    381437
>        105     75962
>        156         4
> 7 samples were bigger than 2551.

That clock steps by 52-53.  There are no hits between o-53 and 53-104 and 
105-156.

On an Intel, I see this histogram:
(i3-2120 CPU @ 3.30GHz)
        ns      hits
        19    489605
        20    412237
        21     62486
        22     35190
        23        63
        24        50
        25        55
        26        50
        27        57
        28        56


-- 
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