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Re: hardware offload (was: Packet number encryption)

"Eggert, Lars" <lars@netapp.com> Sat, 10 February 2018 14:25 UTC

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From: "Eggert, Lars" <lars@netapp.com>
To: Ian Swett <ianswett@google.com>
CC: Christian Huitema <huitema@huitema.net>, "Salz, Rich" <rsalz@akamai.com>, Eric Rescorla <ekr@rtfm.com>, "quic@ietf.org" <quic@ietf.org>, Praveen Balasubramanian <pravb@microsoft.com>
Subject: Re: hardware offload (was: Packet number encryption)
Thread-Topic: hardware offload (was: Packet number encryption)
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Date: Sat, 10 Feb 2018 14:25:39 +0000
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On 2018-2-9, at 13:46, Ian Swett <ianswett@google.com> wrote:
> Hardware acceleration of AES in modern CPUs is extremely good, so another approach is to do the above in a userspace networking stack or the kernel and use the CPU's AES acceleration.  If the networking code that was writing into NIC memory had a deep understanding of QUIC, possibly it could do the packet number encryption as a second pass?

FWIW, this is exactly what I intend on doing with quant, which can sit on top of netmap. At the moment, I do the crypto on the same core as anything else (so I can run-to-completion w/o locks), but eventually I want to try to push things over to other cores for crypto.

I'm also chatting with the Cambridge NetFPGA people to see what type of crypto (and segmentation offload they could provide that would tie in well with a QUIC stack.

Lars

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