Re: IESG Statement On Oppressive or Exclusionary Language

Stewart Bryant <stewart.bryant@gmail.com> Mon, 27 July 2020 19:11 UTC

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From: Stewart Bryant <stewart.bryant@gmail.com>
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Subject: Re: IESG Statement On Oppressive or Exclusionary Language
Date: Mon, 27 Jul 2020 20:11:32 +0100
In-Reply-To: <E7CFDB15-1659-4CB0-BDDF-1DD564207772@akamai.com>
Cc: Stewart Bryant <stewart.bryant@gmail.com>, Joseph Touch <touch@strayalpha.com>, IETF list <ietf@ietf.org>
To: "Salz, Rich" <rsalz@akamai.com>
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> On 27 Jul 2020, at 19:46, Salz, Rich <rsalz@akamai.com> wrote:
> 
> 
>>   The metaphor has to allow arbitrary behaviour of the first stage and zero choice to anything but obedience for the second stage.
> 
> It can be explained in the prose, the words themselves needn't convey that.  To me, and I have no knowledge if that is your intent, this is a way of setting up the discussion so that changing the terms is impossible.
> 

No, I am describing the behaviour of one of the most fundamental hardware components in a computer.

3.3.2 Master–slave edge-triggered D flip-flop <https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Master%E2%80%93slave_edge-triggered_D_flip-flop>

It is the primary technique for crossing synchronisation boundaries.

Interestingly when someone pointed out that slaves occasionally mutinied that aligned the metaphor with greater precision because occasionally the data changes exactly on a clock edge and the flip flop cannot decide which state to adopt in which case it sometimes oscillates for an indeterminate time with catastrophic consequences for the logic. Flip-flop metastability is mitigated by some techniques such as multiple ranking.

The historic term is master-slave, and whilst I condemn this behaviour in humans, it is an accurate metaphor for this electronic construct and the electronics is not offended by this required behaviour.

Stewart